Solid state image sensors are particularly useful for application to household VTR cameras and industrial TV cameras. Particularly, solid state image sensors with a photoconductive film type having the photosensitive section of photoconductive film and processing signals by signal scanning devices fabricated in a silicon substrate are attractive for use especially in small TV cameras on account of their high sensitivity and low smear characteristics.
The dominant Si scanning devices are of the MOS type wherein MOS switching devices are arrayed in matrix and signals are read out from the diode section formed of PN junctions by a shift register, or of the charge transfer type wherein signals are read out by MOS type FETs from the diode section formed on PN junctions to charge transfer devices such as CCDs or BBDs and then fed to the output section.
The present invention particularly concerns the solid state image sensor of the above-mentioned charge transfer type. The general operation of the solid state image sensor of the charge transfer type will first be described.
FIG. 1 is a plan view showing the formation of cells in the solid state image sensor with a photoconductive film type, and FIGS. 2A and 2B are cross-sectional views of a cell each taken along the lines A-B and D-C of FIG. 1, and FIG. 3 is a set of waveform diagrams showing drive pulses for the solid state image sensor shown in FIGS. 1, 2A and 2B. The solid state image sensor with a photoconductive film type shown in FIGS. 1, 2A and 2B has signal read-out MOS FETs formed as buried channels and a vertical transfer stage formed as buried channel CCDs. In the figures, diodes 12 (12a, 12b, 12c) and n-wells 13 (13a, 13b) for the buried channel CCDs are formed on a p-type semiconductor substrate 11. Reference number 14 (14a, 14b, 14c) denotes the channel sections of the buried channel MOS type FETs, and 15 (15a, 15b) is a gate oxide film. Reference number 16 (16a, 16b, 16c) is a set of gate electrodes formed of polycrystalline silicon. The gate electrodes 16 are insulated from an electrode 18 of a photoconductive film 19 by phosphosilicate glass (PSG) layers 17 (17a, 17b). Reference number 20 denotes a transparent electrode which conducts incident light rays l. Reference number 21 denotes one means for changing a voltage applied to the photoconductive film 19. In the instant embodiment, reference number 21 refers to a power source capable of changing a voltage applied to transparent electrode 20. Although the elements 15 and 19 are referred to as films, no substantial difference will arise when they are formed as layers.
Next, an interlace scanning for the foregoing solid state image sensor will be described. For field A, when a signal read-out pulse is applied to the gate electrode 16 at a time t.sub.1 as shown in (a) of FIG. 3, signal charges stored in the photoconductive film 19 and the diodes 12a and 12c are moved to the CCD transfer stage 13b, and the diodes 12a and 12c and the photoconductive film 19 are charged to a certain voltage level (this operation will be termed "reset" and the charging voltage will be termed the reset voltage). Pulses shown in (c) of FIG. 3 are applied to the transparent electrode 20 in order to prevent signal charges in the diodes from being moved to the transfer stage 13b by transfer pulses applied to the electrode 16, and serve to maintain the diode voltage higher by their capacitive coupling during periods other than the reset period. The charges moved to the transfer stage 13b are then transferred at a frequency of 15.75 kHz. In the arrangement of the solid state image sensor shown in FIGS. 1 and 2, the charge transfer stage 13b is provided with potential barrier regions 31a, 31b and 31c and storage regions 30a, 30b and 30c so that the charges are transferred in 2-phase drive mode. The diodes 12a and 12c and the photoconductive film 19 store light signals for one frame period (33.3 ms), then they are reset again. The term "one frame period" may be defined as two vertical scanning periods. The foregoing operation is the signal reading operation for field A. Similarly, field B is reset on expiration of one field period (16.67 ms) and signal charges are read out from the diode 12b and photoconductive film 19. The term "one field period" may be defined as one vertical scanning period.
In the foregoing solid state image sensor with a photoconductive film type employing charge transfer system for interlace scanning, it is unavoidable to have a difference in the reset voltage to the photoconductive film at fields A and B and also a difference in the area of picture elements. These differences lead to the causing of more or less flicker, and it has not been hitherto possible to eliminate such flicker completely. The reset voltage difference (V.sub.nb -V.sub.Na) in the foregoing conventional solid state image sensor can reach 0.5-1.5 V, that is high enough to cause flicker.
When the arrangement of FIG. 1 is operated by the drive pulses shown in FIG. 3, the reset voltage V.sub.N for the photoconductive film can be expressed as follows. ##EQU1## where,
.gamma..sub.i : Rate of change of the maximum channel voltage of the buried channel MOS type FETs to the gate voltage
V.sub.CH : Signal reading voltage
V.sub.pi : Pinch off voltage of the buried channel MOS type FETs
C.sub.t : Sum of the photoconductive film capacitance C.sub.N, diode capacitance C.sub.S and parasitic capacitance C.sub.P
.alpha.: (C.sub.S +C.sub.P)/C.sub.t
.beta.: C.sub.N /C.sub.t
V.sub.Tr : Transfer voltage for the vertical CCD transfer stage
.phi.: Transfer pulse duty cycle for the vertical CCD transfer stage
V.sub.IH : High voltage level of the pulse voltage to the transparent electrode
V.sub.IL : Low voltage level of the pulse voltage to the transparent electrode
Suffix i used in the above equation signifies that the reset voltage V.sub.N varies in each field depending on the values of .alpha. and V.sub.p. Also in equation (1), the 5th and 6th terms of the right side are due to the capacitive coupling between the transfer electrodes 16a and 16b and the electrode 18, and the 5th term represents the modulation component by the transfer pulse and the 6th term represents the effect of voltage drop caused when the signal reading pulse goes off.
The following will describe in connection with FIGS. 1 and 4 the cause of variation in the reset voltage V.sub.N, i.e., variation in .gamma. and V.sub.p of picture elements in two fields, created during the fabricating process of the foregoing solid state image sensor. FIGS. 4(a) through (d) are cross-sectional views of the device essential portions in the fabricating process taken along the lines A-B-C-D of FIG. 1.
First, an n-type impurity, e.g., phosphorous, is doped in the substrate 11 for the n-well 13b of the transferring CCD and the channel sections 14a-14c and diode regions 12a and 12b of the MOS type FET ((a) of FIG. 4). Next, an impurity for compensating the n-type impurity, e.g., boron, is doped selectively with a mask of photoresist 40 in the potential barrier region 13b and channel section 14b of the MOS type FET, so as to form a potential barrier ((b) of FIG. 4). After the gate oxide film 15b and gate electrode 16b are formed, the MOS type FET, and CCD transfer stage of the picture element section for one field are completed ((c) of FIG. 4).
Next, boron is doped in the potential barrier region 31a and channel section 14a of the MOS type FET with one side self-aligned by the gate electrode 16b and another side mask-aligned by the photoresist 41 so as to form a potential barrier. Then a gate oxide film 15a and gate electrode 16a are formed, and the MOS type FETs and CCD transfer stage of the picture element section for another field are completed ((d) of FIG. 4).
As can be seen from the above-mentioned fabricating process, the channel sections 14a and 14b adjoining a MOS type FET correspond to fields A and B, respectively. Since these channel sections are formed by doping an impurity separately, their different doping conditions make it extremely difficult for both channel sections to have an equal pinch off voltage (V.sub.pa =V.sub.pb), and the channel sections 14a and 14b will have different pinch off voltages as shown in (e) of FIG. 4. The gate oxide films 15a and 15b are also formed separately and it is difficult for them to have the same thickness. Consequently, even if the same voltage is applied to the gate electrodes 16b and 16c of the MOS type FETs, the channel sections 14a and 14b will have different potentials, resulting in a difference in the reset voltage to the photoconductive film for fields A and B.
The photocurrent vs. applied voltage characteristic of a usual photoconductive film is shown in FIG. 5, and the quantum efficiency does not reach 1 even by application of a voltage higher than the knee voltage, but instead the photocurrent increases gradually as the applied voltage rises. Therefore, the photosensitivity varies depending on the magnitude of the applied voltage, and if the fields A and B have different reset potentials due to the foregoing reasons, the amount of signal charges created during the storing period varies even under the equal illuminance under which the photoconductive layer would have to create the same amount of signal charges, causing flicker to occur.
In summary, the causes of flicker in the solid state image sensor with a photoconductive film type are, first, the different impurity concentrations in the channel sections of picture elements for fields A and B, and second, the different thicknesses of the gate oxide films of picture elements for fields A and B.
Furthermore, another principal cause of flicker which can be considered is the difference in the area of picture elements for fields A and B. The cause of variation in the picutre element area will be described in connection with FIGS. 2 and 6. FIG. 6 shows the crosssection of the sensor taken along the line E-F of FIG. 1. As shown in the figure, one gate electrode is formed such that its both end portions partly overlie another gate electrode for the purpose of improving the transfer efficiency of the CCD. Due to such arrangement, stepped portions are created differently for each field even by a method of melting the PSG 17 for decrease of their difference, causing the electrode 18 of the photoconductive film 19 formed on the PSG 17 to have a different shape for each field. As a result, photoconductive film 19 may have a different magnitude of area and electrostatic capacity for each picture element. In addition, as shown in FIG. 2A, the thickness of the PSG 17b along the line A-B is smaller than the thickness of the PSG 17a along the line D-C, resulting in a different parasitic capacitance between the gate electrode 16 and the electrode 18 of the photoconductive film in each field. In this case, equation (1) is rewritten as follows. ##EQU2## Here again, suffix i used in the equation signifies that a setup voltage, which means the voltage of the photoconductive film during signal storing period, differs for each field as in the case of equation (1). Due to the difference in the magnitude of picture element area for each field, the amount of signal charges created in the photoconductive film in each field will differ even if the same reset voltage is applied to each field, and flicker cannot be prevented. In addition, the electrostatic capacity C.sub.N of the photoconductive film and parasitic capacitance C.sub.p may vary with each field, making the cause of creating flicker more complicated.
In view of the foregoing prior art deficiencies, it is an object of the present invention to provide a solid state image sensor which prevents flicker by varying the voltage applied to the photoconductive film in the first and second fields for the interlace scanning operation.